Over on the [Behind The Code with Gerry] YouTube channel our hacker [Gerry] shows us how to emulate a 74LS48 BCD-to-7-segment decoder/driver using an Altera CPLD Logic Chip From 1998.
This is very much a das blinkenlights kind of project. The goal is to get a 7-segment display to count from 0 to 9, and that’s it. [Gerry] has a 74LS193 Up/Down Binary Counter, a 74LS42 BCD to Decimal Decoder, and some 74LS00 NAND gates, but he “doesn’t have” an 74LS48 to drive the 7-segment display so he emulates one with an old Altera CPLD model EPM7064SLC44 which dates back to the late nineties. A CPLD is a Complex Programmable Logic Device which is a kind of precursor to FPGA technology.
This fun video runs for nearly one hour and there are all sorts of twists and turns. The clock is made from a 555 timer. The Altera USB Blaster is used to program the CPLD via JTAG. But before he can do that he has to re-enable JTAG on his CPLD because JTAG LOCKOUT has been used on his secondhand chip. JTAG LOCKOUT is something you can do so that you can use the various JTAG pins for other purposes in your design, at the cost of no longer being about to access via JTAG! Fortunately [Gerry] has the right equipment to do a full reset of his chip and thus reinstate JTAG support.
Just as he’s nearly finished his project he manages to short out and destroy his CPLD by dropping a wire into the wall power socket! Talk about unlucky! He has to go back to the drawing board with a similar model. And in the end he realizes he used the the 7447 (common anode) but actually needed the 7448 (common cathode), so he has to fix that up too. All in all it’s fun to see what was state-of-the-art back in 1998. If you’re interested in such things you might like to read Not Ready For FPGAs? Try A CPLD.
